Curriculum Vitae - Manuj Kumar

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1. M AN U J K UM AR m a nuj .k r. g u pt a @ gm ail. c om D -2 3 4 , P a wa n P a t h , ( M) 8 8 24 9 8 5 5 9 7, 0 99 1 1 6 2 0 6 5 1 H a n um a n N a g ar, V a is h a li, J a ip ur O B J E CT I V E To achieve professional satisfaction, career progression and personal development by working in a learning environment that encourages growth and enriches my experience. WORK EXPERIENCE Company: Stellarix Consultancy Services Pvt. Ltd., Jaipur Duration: 23 rd Jul, 2013 to present Designation: Research Analyst (ECE Domain) Job Description & Responsibility: Managing Intellectual Property (IP) related issues Patent searching and analysis of proprietary value including: Patent Landscape State of art Search Patentability/ Novelty Search Invalidation Search Freedom-to-operate Search Infringement Search Claim-Chart Mapping Patent Portfolio Market Research Business Reports Support for patent drafting Preparing various kinds of reports like Infringement Search report, Patent Portfolio, Patentability Search report, FTO Search report, Landscape report, Invalidation Search report, Prior-Art Search report and Non-Patent Literature Search report. Patent Databases: Thomson Innovation, Espacenet, Patentscope, US patents - USPTO, PCT - WIPO, PAJ, KIPRIS, SIPO, AUSPAT etc. Non Patent Databases: Google, Google Scholar, Science Direct, IEEE Xplore, Springer etc. Proficient in Microsoft Excel, Word & Power Point Effective report writing and communication skills Sound leadership and team working qualities Delivering Training (Intellectual Property) & Technical Assistance to new employees 2. EDUCATION Qualification Institute/University Duration Score M.Tech. (Specialization in VLSI Design) Jaypee Institute of Information Technology, Noida 2011-2013 8.4 CGPA B.Tech. (ECE) ABES Engg. Collage, Ghaziabad U.P.T.U. Lucknow 2005-2009 74.24% Intermediate S.B.S.J. Inter Collage, Sambhal 2002-2004 69.6% High School S.B.S.J. Inter Collage, Sambhal 2000-2002 63.33% TECHNICAL EXPERIENCE/PROJECTS 1. RF Interconnect Modeling (M.TECH Major Project) Aim: The aim of the project is to extract or model the on chip VLSI interconnect based on basic principles of electromagnetism which are physical and analytical providing, a physical insight to the factors that affect the interconnect design. Tools Used: ASITIC, FASTHENARY, ADS. This project is a part of NPMASS (National Program on Micro and Smart Systems) program supported by Government of India at MEMS Design Center, JIIT NOIDA in collaboration with IIT Delhi. 2. Design of second generation Current Conveyor (M.TECH Minor Project) 3. Four Degree Freedom Of Robotic Arm (B.TECH Project) PROFESSIONAL SYNOPSIS M.Tech. (Microelectronics and Embedded Technology) professional was associated with Jaypee Institute of Information Technology, Noida as Teaching Assistant with tutorials and guest lectures related to Analog Electronics, Digital Electronics & VHDL. An energetic, self-motivated team member with hands on experience in teaching and material gathering for the proper understanding of subject to the students. SKILLS Hardware Descriptive Languages VHDL (Modelsim 5.5, Xilinx) Circuit Simulators T-Spice, Eldo, H-Spice Layout Tool L-Edit Schematic Capture Tool S-Edit Other EDA Tools ASITIC, ADS, FASTHENARY, emSonnet Languages Known C,C++ Documentation Tools LaTeX/ TeXnic Center, MS Word VLSI, Digital CMOS, Analog CMOS, Embedded System SPICE Coding Programming Skills: C, C++, MATLAB Hardware language: VHDL Coding Top View Simulator, KEIL (8051 assembly language) Linux Administration 3. Hardware implementations of circuits using Bread board. Operating Systems o Windows 98/2000/XP Professional/Vista/Seven TRAINING C, C++ & Data structure Certification from NIIT (16 weeks). 4 Weeks Summer training in Embedded Systems from CETPA InfoTech Pvt. Ltd. Certification in Sun Solaris 10 operating system from Sun Microsystems. Certification in Programmable Logic Controller & HMI/SCADA from Prolific India Pvt. Ltd., Noida. ACHIEVEMENTS AND EXTRACURRICULAR ACTIVITIES Co-hosted SAMVAAD A STUDENT-CORPORATE meets in college. Participated in various quiz, paper presentation and painting competitions. Organized many events in the inter-college fest GENERO09 at ABES. GATE Examination Qualified in 2011 with percentile 93. Attended & presented paper in International Conference MOS-AK/GSA India Workshop JIIT Noida 2012. Presented seminar on RF Interconnects and Signal Integrity Issues at JIIT Noida 2012. PUBLICATIONS Paper published in International Journal & Conferences- 3 1. Manuj Kumar, et.al. Extraction of CMOS VTC with help of NMOS and PMOS output Characteristics through layout net list, International Journal of Information and Computational Technology, ISSN 0974-2255, Volume 2, Number 2 (2012), pp.279-282 2. Manuj Kumar, et.al. Multicore signing off: What is the future , International Conference On "Recent Trends in Electrical and Electronic communication Engineering" at Jawaharlal Nehru University, New Delhi 3. Manuj Kumar, et.al. CMOS Integrated Nano photonics: Feasibility and Challenges Proceedings of International Conference on Mobile and Embedded Technology (MECON 2012), ISBN-978-93-81583-82-1, Amity University Noida. PERSONAL DETAILS Date of Birth: 10 th July 1988 Fathers Name: Mr. Ravindra Kumar Gupta Mothers Name: Late Smt. Shashi Gupta Permanent Address: Moh - Hatim Sarai, Railway Station Road, Sambhal-244302 Present Address: D-234, Pawan Path, Hanuman Nagar, Vaishali, Jaipur-302021 E-Mail: manuj.kr.gupta@gmail.com Languages Known: Hindi & English DECLARATION I, Manuj Kumar, hereby declare that the above information stated by me is true to the best of my knowledge and belief. DATE: 29/04/2015 MANUJ KUMAR